DocumentCode
3332330
Title
Handshaking quasi-adiabatic logic
Author
Chang, Meng-Chou ; Tsai, Chia-Chang
Author_Institution
Dept. of Electron. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan
fYear
2009
fDate
2-5 Aug. 2009
Firstpage
531
Lastpage
534
Abstract
This paper proposes a novel handshaking quasi-adiabatic logic (HQAL) circuit, which combines the advantages of adiabatic logics with those of asynchronous circuits. A HQAL circuit is composed of adiabatic logic blocks and the handshake control chain (HCC). The power of the adiabatic logic blocks in HQAL is controlled and supplied by the HCC, and the logic blocks in HQAL become active only when performing useful computations. With the handshake control chain, the HQAL circuit can avoid the problem of data token overriding, which may occur in conventional asynchronous adiabatic logic (AAL) circuits. Simulation results showed that the HQAL implementation of a pipelined Sklansky adder can achieve 33.1% reduction in power dissipation, compared to the CMOS implementation, for a data rate of 700 MHz and 72.5% reduction in power dissipation for a data rate of 10 MHz.
Keywords
adders; asynchronous circuits; low-power electronics; pipeline processing; HQAL circuit; adiabatic logic block; asynchronous circuit; handshake control chain; handshaking quasiadiabatic logic; low power consumption; pipelined Sklansky adder; power dissipation reduction; Asynchronous circuits; CMOS logic circuits; Clocks; Logic circuits; Logic design; Pipeline processing; Power dissipation; Power supplies; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location
Cancun
ISSN
1548-3746
Print_ISBN
978-1-4244-4479-3
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2009.5236039
Filename
5236039
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