A survey on leakage control techniques in wide-OR domino circuits

Author

Asgari, Farhad Haj Ali ; Ahmadi, Majid ; Wu, Jonathan

Author_Institution

Electr. & Comput. Eng. Dept., Univ. of Windsor, Windsor, ON, Canada

fYear

2009

fDate

2-5 Aug. 2009

Firstpage

459

Lastpage

462

Abstract

In this paper, we compare different existing keeper techniques for reducing power consumption of wide domino logic circuits. We will compare power consumption plus area overhead of each of these methods, with the conventional keeper circuit. A 16-bit multiplexer circuit, in 0.13 mum CMOS technology operating at a frequency of 500 MHz is our test-bench. Simulations show split-domino (SD), with 53% less power consumption, and 10.5% more area, has the best performance.

Keywords

CMOS integrated circuits; leakage currents; logic circuits; logic gates; multiplying circuits; CMOS technology; frequency 500 MHz; leakage control techniques; leakage current; logic circuits; multiplexer circuit; power consumption; simulation; size 0.13 mum; split-domino circuit; wide-OR domino circuits; Circuit noise; Circuit simulation; Energy consumption; Leakage current; Logic circuits; Logic design; Multiplexing; Noise level; Noise reduction; Voltage; Keeper transistor; Leakage current; Wide Domino logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Conference_Location

Cancun

ISSN

1548-3746

Print_ISBN

978-1-4244-4479-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2009.5236057

Filename

5236057