A ΔΣ CMOS ADC with 80-dB dynamic range and 31-MHz signal bandwidth

Author

Aboudina, Mohamed ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA

fYear

2009

fDate

2-5 Aug. 2009

Firstpage

397

Lastpage

401

Abstract

A new SigmaDelta modulator architecture is proposed that shapes DAC mismatches in a manner similar to quantization noise shaping, allowing operation with low oversampling ratios and compact logic. The concept is demonstrated in a fourth-order cascaded system running at a clock frequency of 500 MHz and digitizing input frequencies as high as 31 MHz with 80-dB dynamic range. Fabricated in 90-nm CMOS technology, the prototype provides a peak signal-to-(noise+distortion) ratio of 70 dB at 31 MHz while consuming 140 mW from a 1.2-V supply.

Keywords

CMOS digital integrated circuits; cascade systems; digital-analogue conversion; sigma-delta modulation; signal sampling; CMOS ADC; CMOS technology; DAC mismatch shaping technique; SigmaDelta modulator architecture; bandwidth 31 MHz; fourth-order cascaded system; frequency 500 MHz; power 140 mW; size 90 nm; voltage 1.2 V; Bandwidth; CMOS logic circuits; CMOS technology; Clocks; Dynamic range; Frequency; Noise shaping; Prototypes; Quantization; Shape;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Conference_Location

Cancun

ISSN

1548-3746

Print_ISBN

978-1-4244-4479-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2009.5236070

Filename

5236070