Readout electronics for the FVTX detector at PHENIX

The PHENIX experiment at RHIC at Brookhaven National Laboratory has been providing high quality physics data for over 8 years. The current PHENIX physics program will be significantly enhanced by addition of the Forward Silicon Vertex upgrade detector (FVTX) in the acceptance of existing muon arm detectors. The proposed tracker is planned to be put into operation in FY2011. Each arm of the FVTX detector consist of 4 discs of silicon strip sensors combined with FPHX readout chips, designed at FNAL. Full detector consists of over 1 Million active mini-strip channels with instantaneous bandwidth topping 3.4 Tb/s. The FPHX chip utilizes data push architecture with 2 serial output streams at 200 MHz. The readout electronics design require a split of DAQ into two separate pieces: 1) Read-Out Cards (ROC) located in the vicinity of the detector, 2) Front End Modules (FEM) located in the Counting House. ROC boards, based on the rad-tolerant ACTEL ProAsic3E FPGAs, combine the data from several chips, synchronize data streams and send them to FEM over a Fiber Optics Link. The data are being buffered in the FEM (built on Xilinx Virtex-4 large-scale FPGAs) for 64 consecutive beam crossings and data from appropriate beam bucket are sent to a standard PHENIX DAQ interface upon Level-1 trigger request. I am going to present the current status of the readout electronics development and testing.