Novel 0.44 /spl mu/m/sup 2/ Ti-salicide STI cell technology for high-density NOR flash memories and high performance embedded application

This paper describes the key technology to realize high density flash memory, which has quarter-micron Shallow Trench Isolation (STI), Ti-silicided polycrystalline silicon (poly-Si) gate and source/drain, and tungsten (W) local inter-connect sourceline. Extremely small cell size of 0.44 /spl mu/m/sup 2/ has been obtained with 0.25 /spl mu/m design rule. This cell size is about 30% that of conventional NOR flash cell. To minimize the cell size, the cell gate is patterned with length of 0.25 /spl mu/m, which can be achieved by using channel erasing scheme. STI and 0.15 /spl mu/m floating gate separation can realize a 0.55 /spl mu/m bitline pitch. W sourceline can reduce sourceline resistance and the number of metal sourcelines in the array. In addition, poly-Si gate and active source/drain areas are Ti-silicided at both cells and peripheral transistors, which results in high-speed operation of memory array and peripheral circuits. This high-density NOR cell technology will be essential to realize a low cost and high-performance flash memory and flash embedded logic devices.