DocumentCode
3335891
Title
Evaluation of silicon-on-sapphire enhancement JFETs for digital applications
Author
Talkhan, I.E. ; Abdel-Aty-Zohdy, H.S.
Author_Institution
Dept. of Electr. & Syst. Eng., Oakland Univ., Rochester, MI, USA
fYear
1991
fDate
1-2 Mar 1991
Firstpage
334
Lastpage
335
Abstract
Complete theoretical analysis of SOS n-channel JFET inverter, based on the exact I-V relationship and taking into account the changes in the electron mobility, is presented. A program to implement the analysis is also presented. The simulated results as compared with nMOS inverters resulted in 2.65%, 20% and 80% improvements in the logic swing, pull-up time and power dissipation respectively. A nine-stage ring oscillator is used to rate the performance of the enhancement SOS JFETs for digital applications
Keywords
circuit analysis computing; digital integrated circuits; field effect integrated circuits; integrated logic circuits; junction gate field effect transistors; transient response; DC response; SOS n-channel JFET; Si-Al2O3; digital applications; electron mobility; enhancement JFETs; exact I-V relationship; inverter; program; ring oscillator; CMOS logic circuits; Electron mobility; JFETs; MOS devices; Power dissipation; Pulse inverters; Ring oscillators; SPICE; Stochastic processes; Transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-2170-2
Type
conf
DOI
10.1109/GLSV.1991.143991
Filename
143991
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