Low power folding and interpolating ADC using 0.35-µm technology

Folding and Interpolating ADCs have been shown to be an effective means of digitization of high bandwidth signals at intermediate resolution. The paper focuses on design of low power Folding and Interpolating ADC using novel cascaded folding amplifier. The architecture improvements and optimization of various sub blocks are performed in the paper. The pre processing block-folding amplifier is designed to reduce power consumption and settling time. In ADC, comparators consume the major part of the total power. The converter architecture is designed with reduced number of comparators and minimum hardware. For further reduction of latency and number of comparators, folding amplifier is used in the design of coarse and fine converter both. To reduce the power consumption, encoder based on XOR-OR logic is used. The post simulation results are obtained using 0.35μm technology at 3.3V.