Performance implications of chipset caches in web servers

As Internet usage continues to expand rapidly, careful attention needs to be paid to the design of Internet servers for achieving high performance and end-user satisfaction. In this paper, with the aim of improving memory system performance of Internet servers, we propose and evaluate various design alternatives for "chipset caches", a shared cache layer embedded within a server chipset. Using our trace-based cache simulation framework (CASPER) and SPECweb99 as a representative workload for web servers, we present the performance implications of chipset caches in a front-end dual-processor web server. We start by analyzing the improvement gained by caching the data from processor-initiated requests alone. We study the sensitivity to basic cache parameters (such as cache size and associativity) and also study the impact of prefetching into the chipset cache. We then present the performance implications of routing memory requests initiated by I/O devices through the chipset cache. Finally, we also study the implications of making the chipset cache inclusive. Based on detailed simulation data and its implications on system level performance, this paper shows that chipset caches have significant potential for future Internet servers.