Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model

The traditional analysis of signal delay in a transmission line begins with a lossless LC representation, which yields a wave equation governing the system response; 2-port parameters are typically derived and the solution is obtained in the transform domain. In this paper, we begin with a distributed RC line model of the interconnect and analytically solve the resulting diffusion equation for the voltage response. A new closed form expression for voltage response is obtained by incorporating appropriate boundary conditions for interconnect delay analysis. Calculations of 50% and 90% delay times for various cases of interest (e.g., open-ended RC line) give substantially different estimates from those commonly cited in the literature, thus suggesting revised delay estimation methodologies and intuitions for the design of VLSI interconnects. The discussion furthermore provides a unifying treatment of the past three decades of RC interconnect delay analyses.