DocumentCode
3338855
Title
A universal march pattern generator for testing embedded memory cores
Author
Wang, Wei-Lun ; Lee, Kuen-Jong ; Wang, Jhing-Fa
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
1999
fDate
1999
Firstpage
228
Lastpage
232
Abstract
In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator
Keywords
VLSI; automatic test pattern generation; built-in self test; integrated circuit testing; integrated memory circuits; logic testing; microprocessor chips; BIST; SOC testing; TPG; embedded memory cores; embedded test pattern generator; high fault coverage; memory core testing; multiple march algorithms; system-on-a-chip testing; universal march pattern generator; Built-in self-test; Circuit faults; Circuit testing; Costs; Hardware; Random access memory; Read-write memory; System testing; System-on-a-chip; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location
Washington, DC
Print_ISBN
0-7803-5632-2
Type
conf
DOI
10.1109/ASIC.1999.806510
Filename
806510
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