VLSI interconnect modeling at multi-GHz frequencies incorporating inductance

Due to decreasing device sizes and increasing clock speed, the interconnect delay is the dominant factor in clock skew. This delay has been extracted as the RC component in available EDA tools. In this paper, we model the interconnect as RLC components for systems running at multi-GHz clock speeds. A static extraction analysis method, optimized for VLSI, is detailed which considers all the lines within the vicinity of the target line as return paths. Novel formulas are presented for parallel and series RLC circuit reduction. Results characterization and future research areas are also discussed.