Macromodeling with SPICE for the voltage breakdown behavior in bipolar junction and field-effect transistors

Author

Li, Ye-Ming ; Connelly, J.Alvin

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2003

fDate

23-25 Feb. 2003

Firstpage

166

Lastpage

169

Abstract

This paper presents two macromodels using SPICE primitives to simulate the static current-voltage (I-V) output characteristics of bipolar junction and field-effect transistors (BJTs and FETs) with the collector-emitter and drain-source breakdown voltages taken into account. Both macromodels use a reverse biased diode and a resistor in series with a current-controlled or voltage-controlled voltage source. A practical circuit adopting the macromodel for the BJT (MPSA06) illustrates the voltage-clamped features.

Keywords

SPICE; bipolar transistors; equivalent circuits; field effect transistors; semiconductor device breakdown; semiconductor device models; BJT; FETs; MPSA06; SPICE primitives; bipolar junction transistors; collector-emitter breakdown voltages; current-controlled voltage source; drain-source breakdown voltages; field-effect transistors; macromodels; reverse biased diode; static I-V output characteristics; voltage breakdown behavior; voltage-clamped features; voltage-controlled voltage source; Breakdown voltage; Circuit simulation; Computational modeling; Computer simulation; Dielectric breakdown; Diodes; FETs; Polynomials; Resistors; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 2003. Southwest Symposium on

Print_ISBN

0-7803-7778-8

Type

conf

DOI

10.1109/SSMSD.2003.1190419

Filename

1190419