Vertical double-gate MOSFETs

The downscaling of MOSFET devices will proceed at least for the next 15 years. It is questionable, if the normal, lateral MOSFET can be scaled below 50 nm channel length, which will be reached soon. In this range, the short channel effects, which have been suppressed by improving the lateral bulk MOSFET, demand new device architectures to improve electrical performance. Therefore new layouts as ultra thin body devices and multiple gate MOSFET are developed within the last years. In this work we present a vertical double-gate MOSFET layout, where the current flow is perpendicular to the suiface. For the realization of this layout no SOl-substrate and only one sub-50 nm lithography are needed, resulting in an easier and hence cheaper process flow compared to other multigate layouts. P- and n-channel devices show a transconductance of 150p.SIp.m and 195 μSμm, respectively, and a subthresholdslope S of80 mVidec.