A CPLD-based RC4 cracking system

Author

Kundarewich, Paul D. ; Wilton, Steven J E ; Hu, Alan J.

Author_Institution

Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada

Volume

1

fYear

1999

fDate

9-12 May 1999

Firstpage

397

Abstract

Presents a complex programmable logic device (CPLD) based system for cracking the RC4 (Rivest Cipher 4) encryption algorithm. The system achieves an outstanding price/performance ratio, easily beating other low-cost approaches, such as commodity PCs. The system was implemented using a single Altera EPF10K20 CPLD on an Altera UP1 Education Board. This CPLD is large enough to contain the control unit and five functional units. Measured performance on our prototype shows that we can crack a 32-bit RC4 in an expected time of 15 hours (30 hours worst case). This gives a theoretical expected time of 159 days to crack 40-bit keys-the maximum possible key length that can exported from Canada and the USA. Our results demonstrate the effectiveness of programmable logic (CPLD or FPGA) against even a cryptosystem designed for software implementation.

Keywords

cryptography; performance evaluation; programmable logic devices; 15 to 30 hour; 159 day; Altera EPF10K20 CPLD; Altera UP1 Education Board; CPLD-based RC4 cracking system; FPGA; RC4 encryption algorithm; complex programmable logic device; control unit; cryptosystem; functional units; key length; low-cost approach; performance; price/performance ratio; programmable logic; Cryptography; Educational programs; Field programmable gate arrays; Logic design; Measurement units; Personal communication networks; Programmable logic arrays; Programmable logic devices; Prototypes; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1999 IEEE Canadian Conference on

Conference_Location

Edmonton, Alberta, Canada

ISSN

0840-7789

Print_ISBN

0-7803-5579-2

Type

conf

DOI

10.1109/CCECE.1999.807231

Filename

807231