Partial pre-applied underfill for assembly and reliability of Pb-free CSPs

Author

Morganelli, Paul ; Shah, Jayesh ; Wheelock, Brian ; Mohan, Vinod ; Laffey, Matthew

Author_Institution

Emerson & Cuming Specialty Polymers, Billerica, MA, USA

fYear

2005

fDate

31 May-3 June 2005

Firstpage

223

Abstract

A novel pre-applied underfill is presented. In this approach, a B-staged thermoset is applied to a chip-scale package (CSP) as a thin layer over the solder bump array. During reflow, the coating expands to fill the standoff gap between the PCB and package, providing reinforcement to the solder joints. The underfill material is stable at typical drying and burn-in conditions, allowing it to be applied early in the manufacturing process. The expanded underfill was found to improve drop impact resistance significantly relative to a non-underfilled CSP.

Keywords

assembling; chip scale packaging; coatings; impact (mechanical); integrated circuit reliability; polymers; reflow soldering; B-staged thermoset; CSP; Pb; assembly; chip-scale package; drop impact resistance; manufacturing process; pre-applied underfill; reflow soldering; reliability; solder bump array; solder joints; Assembly; Biological materials; Cellular phones; Chip scale packaging; Coatings; Electronics packaging; Manufacturing processes; Moisture; Polymers; Soldering;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2005. Proceedings. 55th

ISSN

0569-5503

Print_ISBN

0-7803-8907-7

Type

conf

DOI

10.1109/ECTC.2005.1441270

Filename

1441270