Electrical characterization and modeling technique for substrate designs

Future digital systems require the interconnection of cost competitive, functional components with high performance, high functionality and high reliability. To achieve these requirements, high density CMOS integrated circuits require high performance single chip packages. The electrical design of these packages require the careful co-design of the power and signal distribution within the package. An electrical characterization and modeling technique for proper analysis of the power and signal distribution design in the component´s substrate is described in the context of the overall sub-system infrastructure. The measurement technique includes the design of a test fixture that facilitates the characterization process while maintaining reasonable accuracy.