DocumentCode
3348265
Title
Verifiable Template Development for HDL-Descriptions
Author
Syrevitch, Yevgeniya ; Zinchenko, Dariya
fYear
2007
fDate
19-24 Feb. 2007
Firstpage
136
Lastpage
138
Abstract
Classification of digital devices by types of their language descriptions is introduced in the paper. Also, a template of HDL-model of digital device, which will fit verification objectives in a case of using path sensitization methods, is considered.
Keywords
digital circuits; hardware description languages; HDL-model; digital devices; language descriptions; path sensitization methods; verifiable template development; verification objectives; Arithmetic; Automata; Data processing; Design automation; Digital circuits; Hardware design languages; Iron; Logic devices; Process design; Testing; design-for-verification; functional verification; graph model; hardware description language; path sensitization;
fLanguage
English
Publisher
ieee
Conference_Titel
CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of
Conference_Location
Lviv-Polyana
Print_ISBN
966-533-587-0
Type
conf
DOI
10.1109/CADSM.2007.4297503
Filename
4297503
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