Hardware Realization of the AES Algorithm S-Block Functions in the Current-Mode Gate Technology

In this paper, the new approach to minimization of logic functions in the current-mode gate algebra is proposed. The main purpose is reduction of the current-mode circuit hardware overhead in such a way, that chip area needed for realization of the current-mode circuits will not greater than the chip area needed for realization of similar circuits with the classical CMOS. The approach is based on the analysis of the given truth table of the target function for searching the fragments, which correspond to selected types of sub-functions, which are hardly minimized in the Boolean algebra, but are simpler minimized in the current-mode gate algebra. The correctness and efficiency of the proposed approach are proved during design of the current- mode circuits destined for realization of several functions of the S-blocks in the AES cryptographic algorithm.