Design of a High-Temperature, Space Efficient Digital Filter on an FPGA

This paper outlines the design of a space-efficient digital filter for use in high-temperature FPGA applications. It presents three different methods of implementing a Butterworth filter design using VHDL: bit serial, shared multiplier and single step. It outlines the main signals and states used in these designs. The bit-serial approach uses bit-serial arithmetic for the filter equation instead of combinational adders and multipliers. This filter design is the slowest in processing the data, and is not very efficient in terms of flip-flops or overall space usage. The shared multiplier design uses a single multiplier for each multiplication in the equation. The design is the smallest of the three. The single step design calculates the filter equation in one step using multiple adders and multipliers. This design uses the least number of flip-flops. The results obtained by implementing these designs on a FPGA are also presented. The shared multiplier and the single step approach are both efficient depending on the resource in demand on the FPGA. The bit serial approach is not useful for space efficient designs