Timing optimization of MOS combinational networks

The authors extend their MOS network optimization algorithm, SYLON-REDUCE, to perform timing optimization. Since optimization is performed in a technology-specific domain, the results should more closely reflect the actual improvement in the delay of the network. They also propose a delay model that takes into account the largest number of serially-connected transistors, as well as the number of fanouts, of each gate in the network. Using this delay model seems to generally yield the best results. The authors´ algorithm allows the number of transistors in a cell to increase during resynthesis, though it almost always finds a smaller network. Their results compare favorably with those of SYLON-DREAM and MIS