DocumentCode
3352041
Title
A BIST algorithm for bit/group write enable faults in SRAMs
Author
Adham, Saman ; Nadeau-Dostie, Benoit
Author_Institution
LogicVision, Inc., San Jose, CA, USA
fYear
2004
fDate
9-10 Aug. 2004
Firstpage
98
Lastpage
101
Abstract
The use of group (or bit) write enable in memories is becoming very common in embedded memories. The circuitry used to achieve these functions need be thoroughly tested for different kind of defects using specific test sequence. However, most BIST algorithms assume that these write enables are forced active during the global write cycle in the BIST run. This paper presents a serial interface BIST algorithm that is used to test defect on bit/group write enables of these memories.
Keywords
SRAM chips; built-in self test; embedded systems; integrated circuit testing; BIST algorithm; SRAM; embedded memories; global write cycle; test sequence; write enable fault; Built-in self-test; Circuit faults; Circuit testing; Decoding; Electrical fault detection; Fault detection; Random access memory; SRAM chips; System-on-a-chip; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on
ISSN
1087-4852
Print_ISBN
0-7695-2193-2
Type
conf
DOI
10.1109/MTDT.2004.1327991
Filename
1327991
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