Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down

Among various decoding algorithms of Reed-Solomon (RS) codes, algebraic soft-decision decoding (ASD) can achieve significant coding gain with polynomial complexity. One major step of ASD is the interpolation. The interpolation problem can be solved by the Nielsonpsilas algorithm, which involves discrepancy coefficient computation. This computation requires a feedback loop with one multiplier, one adder and one register. The maximum clock frequency of the interpolation architecture is limited by the multiplier-adder path in this loop. In this paper, we propose to employ the slow-down technique to increase the register number in the feedback loop, such that the multiplier-adder path can be divided into shorter segments through retiming to achieve higher clock frequency. In addition, input sequences to the feedback loops are interleaved. Applying the proposed interpolation architecture to a (255, 239) RS code with maximum multiplicity three, 43% higher efficiency in terms of speed/area ratio can be achieved over prior efforts.