• DocumentCode
    3355353
  • Title

    Identification of process variables affecting the quality of fine pitch high performance ASIC substrates

  • Author

    Bay, Emilia ; Bhatt, Ash ; Keesler, Ross ; Konrad, John ; Sebesta, Robert

  • Author_Institution
    Endicott Interconnect Technol. Inc., NY, USA
  • fYear
    2005
  • fDate
    31 May-3 June 2005
  • Firstpage
    1506
  • Abstract
    The HyperBGA® semiconductor package is a PTFE based organic flip chip designed to meet the needs of high performance applications. It combines outstanding overall reliability with higher electrical performance to distinguish itself from wirebond applications, build-up technology, and ceramic alternatives. Signal layers are personalized with high wiring density and wire width ranging from 20 to 33 microns. At this time only a liquid photolithographic process can be used to resolve these ultradense fine lines and spaces while also achieving very tight impedance control. Yields thru automated optical test (AOI) test are mostly impacted by non-repairable defects as circuit opens, neckdowns and dishdowns type defects. To improve on existing yield targets, the entire photolithographic process was considered, examined and variables investigated. Higher yielding processes are absolutely critical for next generation design points. In this article, the photo process and operative variables are discussed with regard to their impact on fine line quality, yields and high reliability of the product in the field.
  • Keywords
    application specific integrated circuits; ball grid arrays; flip-chip devices; integrated circuit reliability; integrated circuit yield; optical testing; photolithography; AOI test; ASIC substrates; HyperBGA® semiconductor package; PTFE; automated optical test; electrical performance; fine pitch; high wiring density; impedance control; non-repairable defects; organic flip chip; photolithographic process; signal layers; ultradense fine line; wirebonding; yielding process; Application specific integrated circuits; Automatic testing; Ceramics; Circuit testing; Flip chip; Semiconductor device packaging; Space technology; Substrates; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2005. Proceedings. 55th
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-8907-7
  • Type

    conf

  • DOI
    10.1109/ECTC.2005.1441987
  • Filename
    1441987