High performance service-time-stamp computation for WFQ IP packet scheduling

Author

McKillen, C. ; Sezer, S. ; Xin Xang

Author_Institution

Inst. of Electron., Commun. & Inf. Technol., Belfast

fYear

2006

fDate

2-3 March 2006

Abstract

In this paper the design and implementation of a unique service-time-stamp computation circuit, called the finishing tag, for WFQ based packet scheduling is presented. The implementation is based on UMC 130nm standard cell technology, and placed and routed using Cadence SoC encounter. The design targets the development of programmable IP packet scheduling circuits for next generation network processing platforms for line-rates beyond 200Gbps

Keywords

IP networks; processor scheduling; programmable circuits; queueing theory; system-on-chip; telecommunication traffic; 130 nm; Cadence SoC; UMC standard cell technology; WFQ IP packet scheduling; finishing tag; network processing platforms; programmable IP packet scheduling circuits; service-time-stamp computation circuit; weighted fair queuing; Circuits; Finishing; Global Positioning System; High performance computing; Next generation networking; Quality of service; Round robin; Scheduling algorithm; Telecommunication traffic; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on

Conference_Location

Karlsruhe

Print_ISBN

0-7695-2533-4

Type

conf

DOI

10.1109/ISVLSI.2006.49

Filename

1602419

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3358399