A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control

Author

Choi, Moo-Yeol ; Lee, Sung-No ; You, Seung-Bin ; Yeum, Wang-Seup ; Park, Ho-Jin ; Kim, Jae-Whui ; Lee, Hae-Seung

Author_Institution

Samsung Electron., Yongin

fYear

2008

fDate

21-24 Sept. 2008

Firstpage

89

Lastpage

92

Abstract

A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm². A post integration time control (PITC) technique is proposed for calibration of the RC time constant variation of the continuous-time integrator. In addition, a jitter insensitive pulse generator (JIPG) circuit overcomes the degradation of SNR due to the feedback DAC clock jitter. The measured SNR and DR are 101 dB and THD is -94 dB.

Keywords

CMOS integrated circuits; analogue-digital conversion; jitter; pulse generators; CMOS process; continuous-time integrator; hybrid delta-sigma audio ADC; jitter insensitive pulse generator circuit; noise figure 101 dB; post integration time control; Clocks; Feedback circuits; Filtering; Filters; Jitter; Pulse generation; Radio control; Scalability; Switched capacitor circuits; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-2018-6

Electronic_ISBN

978-1-4244-2019-3

Type

conf

DOI

10.1109/CICC.2008.4672028

Filename

4672028