A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration

A variable-gain amplifier (VGA) with pseudo-random noise (PN) signal-dependent dithering and chopping is proposed. It allows the ADC gain and offset errors to be calibrated digitally in background. A 10~15 b 60 MS/s floating-point ADC (FADC) with variable gains from 1 to 32 enhance the INL from 24 to 0.9 LSB at 15 b level. Its non-linearity resulting from the VGA gain and offset errors is eliminated after calibration. A chip in 0.18 mum CMOS occupies 3.5 x 2.5 mm² and consumes 300 mW at 1.8 V.