Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS

Author

Kotaki, H. ; Kakimoto, S. ; Nakano, M. ; Matsuoka, T. ; Adachi, K. ; Sugimoto, K. ; Fukushima, T. ; Sato, Y.

Author_Institution

Central Res. Labs., Sharp Corp., Nara, Japan

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

459

Lastpage

462

Abstract

We have developed a high speed dynamic threshold voltage MOSFET named B-DTMOS for ultra low power operation. This was realized using a bulk wafer containing an individual trench isolated shallow-well with a high concentration buried layer sandwiched between two low concentration layers surrounded by a deep well. The B-DTMOS achieved an excellent propagation delay time of 83.6 psec at 0.6 V operation and 103.3 psec at 0.5 V operation. This was realized due to ultra low body resistance of the B-DTMOS.

Keywords

CMOS integrated circuits; MOSFET; buried layers; delays; isolation technology; leakage currents; 0.5 V; 0.6 V; 103.3 ps; 83.6 ps; B-DTMOS; SITOS isolation; bulk dynamic threshold voltage MOSFET; bulk wafer; deep well; gate to shallow-well contact process; high concentration buried layer; high speed dynamic threshold voltage MOSFET; junction leakage current; low concentration layers; propagation delay time; trench isolated shallow-well; ultra low body resistance; ultra low power dual gate CMOS; Batteries; Delay; Fabrication; Immune system; Leakage current; MOSFET circuits; Power MOSFET; Power dissipation; Power supplies; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.553626

Filename

553626