DocumentCode
3360115
Title
Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects
Author
Thacker, Hiren D. ; Meindl, James D.
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
fYear
2006
fDate
Oct. 2006
Firstpage
1
Lastpage
7
Abstract
Gigascale (GSI) chips with high-bandwidth, integrated optoelectronic (OE) components are an emerging technology. This paper identifies the issues related to testing of such chips during high-volume manufacturing. A probe substrate to enable the same is also demonstrated
Keywords
integrated circuit testing; integrated optoelectronics; production testing; gigascale chips; high-volume manufacturing; integrated optoelectronic; optical I/O interconnects; probe substrate; wafer-level testing; CMOS technology; High speed optical techniques; Integrated circuit interconnections; Logic devices; Logic testing; Optical devices; Optical interconnections; Optical modulation; Optical receivers; Optical transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2006. ITC '06. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
1-4244-0292-1
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2006.297668
Filename
4079346
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