Seamless Integration of SER in Rewiring-Based Design Space Exploration

Author

Almukhaizim, Sobeeh ; Makris, Yiorgos ; Yang, Yu-Shen ; Veneris, Andreas

Author_Institution

Dept. of Electr. Eng., Yale Univ., New Haven, CT

fYear

2006

fDate

Oct. 2006

Firstpage

1

Lastpage

9

Abstract

Rewiring has been used extensively for optimizing the area, the power consumption, the delay, and the testability of a circuit. In this work, we demonstrate how rewiring can also be used for reducing the soft error rate (SER). We employ an ATPG-based rewiring method to generate functionally-equivalent yet structurally-different implementations of a logic circuit based on simple transformation rules. This rewiring capability, along with an off-the-shelf method for assessing the SER of a circuit, enable the integration of the SER in a unified search algorithm that iteratively evolves the design in order to satisfy a given set of objectives. Experimental results on ISCAS´89 and ITC´99 benchmark circuits verify that rewiring can indeed be successfully used to reduce the SER of a circuit and, thus, it facilitates a design-space exploration framework for trading off area, power consumption, delay, testability, and SER

Keywords

automatic test pattern generation; integrated circuit design; integrated circuit testing; integrated logic circuits; logic design; logic testing; ATPG-based rewiring; ISCAS´89; ITC´99; circuit area optimization; circuit delay; circuit testability; logic circuit; power consumption; rewiring-based design space exploration; soft error rate; Algorithm design and analysis; Benchmark testing; Circuit testing; Delay; Energy consumption; Error analysis; Iterative algorithms; Logic circuits; Power engineering computing; Space exploration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2006. ITC '06. IEEE International

Conference_Location

Santa Clara, CA

ISSN

1089-3539

Print_ISBN

1-4244-0292-1

Electronic_ISBN

1089-3539

Type

conf

DOI

10.1109/TEST.2006.297682

Filename

4079360