A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode

A voltage scalable 0.26 V, 64 kb 8 T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Reverse short channel effect was utilized to improve cell write margin and read performance. A marginal bitline leakage compensation scheme was used during read operation to lower V_min down to 0.26 V. Floating write bitline and read bitline, auto wordline pulse width control, and a deep sleep mode minimize the active and standby leakage power consumption.