DocumentCode
3360920
Title
Variable block size motion estimation algorithm and its hardware architecture for H.264/AVC
Author
Lee, Jae Hun ; Lee, Nam Suk
Author_Institution
Digital Media R&D Center, Samsung Electron. Co., Ltd., South Korea
Volume
3
fYear
2004
fDate
23-26 May 2004
Abstract
This paper presents a variable block size motion estimation (ME) algorithm and its hardware architectures dedicated to H.264/AVC. Proposed ME architecture can achieve real-time processing for 720×480@30Hz with search range of [-64, +63] in the horizontal and [-32, +31] in the vertical direction at integer-pel accuracy and upto 7 reference frames at the operating frequency of 54MHz.
Keywords
motion estimation; real-time systems; telecommunication standards; video coding; 54 MHz; AVC; H.264; hardware architecture; integer-pel accuracy; real-time processing; reference frames; variable block size motion estimation; Automatic voltage control; Filtering; Hardware; IEC standards; ISO standards; MPEG 4 Standard; Merging; Motion estimation; Research and development; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1328853
Filename
1328853
Link To Document