Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage

A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques. The proposed CMOS ring oscillator is designed and implemented with a charge-pump based phase-locked loop in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 4-GHz output clock is reduced from 10.66-ps to 5.04-ps while subject to switching noise with magnitude of 2.5% of the supply voltage at 150-MHz. Furthermore, more than 4.5times of reduction in the power consumption is achieved.