A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor

This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration. The prototype is fabricated in a 0.18-mum CMOS process. The implemented DVS circuit provides a supply voltage from 1.4 V to 1.8 V and the DFS circuit dynamically generates the system clock from 7.5 MHz to 120 MHz according to the workload of the embedded processor. The DVS and DFS circuits occupy 2.72 mm² and 0.27 mm² active areas, respectively.