Session 21 - Leveraging the third Dimension

Leveraging the 3^rd Dimension by stacking silicon and assembling it into a single package is already underway in the miniaturization of consumer electronics and more. This session will address the mature package level wire-bond-3D stack, mature multi-chip package, and the silicon level 3D stack enabled by Through-Silicon-Via (TSV). The reasons for moving to TSV-3D are driven by some of the major challenges introduced with process scaling and/or complex SOCs such as leakage/power, interconnect delay, bandwidth/performance, non-optimum process technology, memory, and circuits resistant to scaling.