Characterization of random decision errors in clocked comparators

Clocked comparators have found widespread use in noise sensitive applications such as wireline receivers, A/D converters, and memory bit-line detectors. However, their nonlinear, time-varying behavior and discrete output levels have discouraged the use of traditional small-signal noise simulation techniques such as NOISE in SPICE. This paper asserts that the periodic noise analysis available from RF circuit simulators can provide insight into the intrinsic sampling and decision operations of clocked comparators and help develop a linear periodically time-varying (LPTV) noise model that accurately predicts the decision error probability. Two comparators are simulated and compared to laboratory measurements. A 90 nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mVrms for DC inputs, matching simulation results with a short channel excess noise factor gamma = 2.