Package-level thermal management of a 3D embedded wafer level package

As the embedded wafer-level packaging (eWLP) technology evolves to capitalize on package-on-package (POP) technology, thermal analysis has been performed to investigate and improve the heat dissipation capability of the 3D package structure. 3D simulation models have been built to study the impact of the thermal properties (underfill material, passivation layer and mold compound) and geometries (over mold, passivation layer and Cu layer in RDL) on the package thermal performance. We also analyzed the thermal effect of the Cu percentage in each RDL layer. The top heat spreader, thermal via arry, bottom heat dissipation plate and two types of top thermal cases have employed to enhance the heat dissipation capability. In baseline conditions, without any enhancement structure, the 85°C temperature limit can be met, at a max total PoP power dissipation of 2W (Logic: 1.5W, memory: 0.5W). In the mobile device scenario, passive cooling solutions have been applied to the PoP structure, and a total power of 4W can be accommodated with the proposed cooling structures.