An all-digital direct digital synthesizer fully implemented on FPGA

In this paper an all-digital pulse output direct digital synthesizer (DDS) is described. The synthesizer is fully implemented on FPGA and does not require any external analog components. Selective over-sampling and tapped delay line are used to reduce jitter and improve spectral performance. Selective over-sampling relaxes the requirements on the delay line with a minor effect on power consumption and circuit complexity. The delay line is implemented using the FPGA digital clock manager (DCM). The synthesizer generates clock signals with maximum output frequency up to f_clk. It achieves sub-Hz resolution and sub-¿s switching time. Experimental measurements validate system operation with spurious free dynamic range (SFDR) greater than 40 dB.