FinFET SRAM Process Technology for hp32 nm node and beyond

Progresses in FinFET SRAM process technology are reviewed. The process technologies discussed in this paper are narrow and uniform fin formation, reduction of source/drain parasitic resistance, gate stack for threshold voltage control, integration scheme to build FinFET and planar FET on a wafer, and fin height tuning technique for beta-ratio control. These technologies are considered to enable the FinFET to become a prospective device for future SoC applications. Furthermore, FinFET future prospects are also presented.