Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects

This paper investigates the impact of signal rise and fall time variations on voltage overshoot and propagation delay in inductive lines for different switching patterns. Equivalent circuit model parameters have been extracted using FastCap and FastHenry field solvers; and results have been obtained by HSpice simulator. Most existing works study the impacts of different switching patterns considering only a constant rise/fall time. However, here it is observed that decreasing rise/fall time alters the inductive behavior under different switching patterns. The investigation in this paper reveals that switching patterns start showing significant impact for a particular range of rise and fall times.