Efficiently searching the optimal design space

Author

Blythe, Stephen A. ; Walker, Robert A.

Author_Institution

Dept. of Comput. Sci., St. Louis Univ., MO, USA

fYear

1999

fDate

4-6 Mar 1999

Firstpage

192

Lastpage

195

Abstract

One of the primary advantages of a high-level synthesis system is its ability to explore the design space. This paper presents several methodologies for design space exploration that compute all optimal tradeoff points for the combined problem of scheduling, clock length determination, and module selection. We discuss how each methodology takes advantage of both the structure within the design space itself as well as the structure of, and interaction between, each of the three subproblems

Keywords

VLSI; circuit optimisation; clocks; high level synthesis; integrated circuit design; scheduling; clock length determination; design space exploration; high-level synthesis system; module selection; optimal design space; optimal tradeoff points; scheduling; subproblems; Clocks; Computer science; Delay; Design methodology; High level synthesis; Knee; Process design; Processor scheduling; Space exploration; Time factors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757408

Filename

757408

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=336502