A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique

In phase-locked loop (PLL), the loop parameters such as loop bandwidth, phase margin and damping factor must be adjusted to minimize jitter and to guarantee stability. According to the restrictions of the PLL, this paper employs formula derives to find the relationship between the loop parameters. Therefore, the PLL uses time-to-digital converter (TDC) and programmable current mirror (PCM) to adjust loop parameters that can apply to provide the wide operating frequency range and low-jitter performance. The chip is fabricated in a 0.18-mum standard CMOS process with a 1.8 V power supply voltage and consumes 8 mW at 400 MHz operation frequency. The measured output operating frequency range is 100 MHz-1 GHz, the input reference frequency range is 5 MHz-100 MHz, and the jitter is less than 3.3 % of the output period.