Highly linear wideband low power current mode LNA

This paper presents design considerations for low power, highly linear current mode LNAs that can be used for wideband RF front-ends for multi-standard applications. The circuit level simulations of the proposed architecture indicate that with optimal biasing a high value of IIP3 can be obtained. A comparison of three scenarios for optimal bias is presented. Simulation results indicate that with the proposed architecture, LNAs may achieve a maximum NF of 3.6 dB with a 3 dB bandwidth larger than 10 GHz and a best case IIP3 of +17.6 dBm with 6.3 mW power consumption. The LNAs have a broadband input match of 50 Omega. The process is 90 nm CMOS and with 1.1 V supply the LNAs power consumption varies between 6.3 mW and 2.3 mW for the best and the worst case IIP3, respectively.