Investigations and measurements of the dynamic performance of high speed ADCs

Investigations concerning the origin of the aperture jitter in a 4-b parallel analog-to-digital converter (ADC) implemented in a 0.5-μm GaAs FET technology have been undertaken. On-chip electron-beam measurements of the comparator clock distribution show a deviation of 20 ps between the comparators. Simulation considering process variations shows similar results. To overcome these problems, a GaAs 5-b, 1-Gsamples ADC with on-chip track-and-hold circuitry (T&H) has been developed. A complete DC and AC characterization of the ADC using a histogram test, fast Fourier transform test, sine wave curve-fitting test and beat frequency test up to 1.3 GHz was performed. The measurement set-up consisted of a 4-GHz sine wave generator, a 10-GHz pulse generator, an 8-b wide 700-MHz digital acquisition system for data recording, and a PC. By using the T&H in front of the parallel ADC, 4.6 effective number of bits (ENOB) has been achieved at 1-GHz input signal compared to 3.7 ENOB without T&H. A comparison of the different test methods and results is given