Phased tag cache: an efficient low power cache system

In this paper, we propose a low power cache design, namely phased tag cache, for reducing the power consumption of set-associative caches. In the phased tag cache, the tag is compared in two phases. A small part of the tag is compared in the first phase to determine the data way which a memory reference falls into. The remaining bits of the tag are compared in the second phase to verify if the result from the first phase is valid. By doing so we can eliminate most of the unnecessary activities on the entire tag. We used the CACTI cache model to show that the time overhead of the phased tag cache is small. Simulation results based on Spec2000 benchmark applications suggest that the phased tag cache design has small impact on the cache performance. The power model shows the phased tag design reduces the power consumption by 30-50%, compared to conventional caches used by the Itanium2 processor.