Monitoring gate and interconnect delay variations by using ring oscillators

With process variability increasing in advanced processes, it becomes more challenging to diagnose or debug a low-yield problem. For finding out the root causes of a low-yield problem, currently we rely on limited process data provided by foundries or diagnosis tools and physical failure analysis (PFA). Only relying on defect diagnosis analysis and PFA is not sufficient to quickly conclude with a specific process problem. For gathering more information about a process, we propose to embed a process monitor consisting of ring oscillators in a circuit. Our proposed monitor design can monitor both gate and interconnect delay variation. A comprehensive simulation has been conducted and the silicon results will be shown in this paper.