An all-digital on-chip jitter measurement circuit in 65nm CMOS technology

Author

Chung, Ching-Che ; Chu, Wei-Jung

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Min-Hsiung, Taiwan

fYear

2011

fDate

25-28 April 2011

Firstpage

1

Lastpage

4

Abstract

An all-digital built-in jitter measurement (BIJM) circuit is presented in this paper. A frequency divider is taken as a timing amplifier to linearly amplify the input jitter. Subsequently, a vernier ring oscillator (VRO) is used as a time-to-digital converter (TDC) to quantize the jitter information into digital codes. The proposed self-referred architecture with a cycle-controlled delay line doesn´t require an external reference clock to measure the jitter of the on-chip signals. Therefore, the BIJM circuit design complexity is greatly reduced by the proposed architecture. The proposed all-digital BIJM is implemented in a 65nm CMOS process, and the input frequency range is 100MHz to 300MHz.

Keywords

CMOS analogue integrated circuits; UHF amplifiers; UHF oscillators; frequency dividers; timing jitter; BUM; CMOS process; CMOS technology; SoC; TDC; VRO; all-digital on-chip built-in jitter measurement circuit; cycle-controlled delay; frequency 100 MHz to 300 MHz; frequency divider; size 65 nm; time-to-digital converter; timing amplifier; vernier ring oscillator; Clocks; Frequency conversion; Jitter; Phase locked loops; Radiation detectors; System-on-a-chip; Timing; clocks; jitter; oscillator; vernier ring oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Conference_Location

Hsinchu

ISSN

Pending

Print_ISBN

978-1-4244-8500-0

Type

conf

DOI

10.1109/VDAT.2011.5783605

Filename

5783605