Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems

Time interleaved A/D converters (TIADCs) provide an attractive solution to the realization of analog front ends in high speed communication systems. However, gain mismatch, offset mismatch, and sampling time mismatch between time-interleaved channels limit the performance of TIADCs. This paper presents a low-cost test scheme to measure timing mismatch using an undersampling clock. Our method is applicable to an arbitrary number of channels, achieving picosecond resolution with low power consumption. Both simulation and hardware measurements are presented to validate the proposed technique.