Design and implementation of basic building blocks of FPGA using memristor-transistor hybrid approach

In view of the challenges faced to minimize the gap between FPGA and ASIC, this paper primarily focuses on the area and power efficiency improvement of FPGA using memristor-transistor hybrid approach. A lot of research has been carried out in the field of FPGA that has focused on decreasing the gap between FPGAs and ASICs. However, still FPGAs are larger in area, slower in speed and more power consuming than their ASIC counterparts. In this work, basic building blocks like MUX, NOR gate, D flip flop and NOT gate are designed and implemented using memristor-transistor hybrid approach. These basic building blocks are combined to form Configurable Logic Blocks (CLBs), Switch Boxes (SBs) and Connection Boxes (CBs) of FPGA. Proposed basic building blocks of FPGA are smaller in size as compared to the conventional building blocks. These building blocks when combined together will eventually reduce the overall size of FPGA and lower its power consumption.