A 10-bit 1kS/s-30kS/s successive approximation register analog-to-digital converter for biological signal acquisition

This paper presents an ultra-low power successive approximation register analog-to-digital converter (SAR ADC) which works as a part of the biological signal acquisition system. The power supply voltage is decreased by utilizing bootstrapped switches. Binary weighted capacitor array is adopted to simplify the design and reduce the power dissipation of the control logic. The switching scheme ensures full-range sampling and avoids the dynamic offset of the comparator. Post-simulation results show that this ADC achieves the SNDR of 60.52dB at a sampling rate of 1kS/s. The power consumption is 130nW with a 1.2V power supply. This chip is fabricated in 0.18-μm TSMC 1P6M CMOS process and the die area is 1.4mm×1.4mm.