DocumentCode
3374320
Title
A comparative study of the quasi-saturation in the high voltage vertical DMOS for different cell geometries
Author
Zhu, Ronghua ; Chow, T.P.
Author_Institution
Rensselaer Polytech. Inst., Troy, NY, USA
fYear
1998
fDate
3-6 Jun 1998
Firstpage
343
Lastpage
346
Abstract
The quasi-saturation behaviour of the high voltage vertical power DMOSFET is studied for the stripe, hexagonal and atomic-lattice-layout designs. The experimental results show that the device enters into quasi-saturation at different gate voltages for these cell designs. Numerical device simulations show that it is due to different JFET and drift-region resistances associated with these designs
Keywords
electric resistance; numerical analysis; power MOSFET; semiconductor device models; semiconductor device testing; JFET resistance; atomic-lattice-layout design; device quasi-saturation; drift-region resistance; gate voltages; hexagonal design; high voltage vertical DMOSFET; high voltage vertical power DMOSFET; quasi-saturation; quasi-saturation behaviour; stripe design; vertical DMOS cell geometries; Circuit simulation; Geometry; MOSFET circuits; Manufacturing; Numerical simulation; Power MOSFET; Power electronics; Switches; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on
Conference_Location
Kyoto
ISSN
1063-6854
Print_ISBN
0-7803-4752-8
Type
conf
DOI
10.1109/ISPSD.1998.702708
Filename
702708
Link To Document